A Foldback Current Limiting Circuit for Voltage Regulator

A fold-back current limiting circuit for a voltage stabilizer is connected to the output end of the voltage stabilizer and comprises PMOS transistors P2, P3 and P4, an NMOS transistor N1 and resistors R3 and R4. Source electrodes and substrates of the PMOS transistors P2, P3 and P4 are all connected with a power source VDD, a grid electrode of the PMOS transistor P2 is connected with the output end of a differential amplifier EA in the voltage stabilizer, a drainelectrode of the PMOS transistor P2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with one end of the resistor R4 and a grid electrode of the NMOS transistor N1. The other end of the resistor R4 is grounded, a source electrode of the NMOS transistor N1 is connected with the output end OUT of the voltage stabilizer, a drain electrode of the NMOS transistor N1 is connected with a drain electrode and a grid electrode of the PMOS transistor P3, the drain electrode of the NMOS transistor N1 and a grid electrode of the PMOS transistor P4 are connected together, a substrate of the NMOS transistor N1 is grounded, and a drain electrode of the PMOS transistor P4 is connected with the output end of the differential amplifier EA in the voltage stabilizer.